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SA306 Datasheet(PDF) 9 Page - Cirrus Logic |
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SA306 Datasheet(HTML) 9 Page - Cirrus Logic |
9 / 14 page SA306 SA306U P r o d u c t I n n o v a t i o n F r o m SGND Gate Control Vs OUT A PGND At Ab SC TEMP SC Logic Temp Sense Ref Ia DIS2 I LIM/DIS1 UVLO Ia' Lim b Lim c + _ Vdd Lim a Current Sense 12k 12k 12k 12k Vth The block diagram in Figure 5 illustrates the features of the input and output structures of the SA306. For simplicity, a single phase is shown. FIgURE.INPUTANDOUTPUTSTRUCTURESFORASINgLEPhASE TABLE2.TRUThTABLE Comments 0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off. 0 1 <V th 0 0 PGND Bottom output FET for that phase is turned on. 1 0 <V th 0 0 VS Top output FET for that phase is turned on. 1 1 X X X High-Z Both output FETs for that phase are turned off. X X >V th 1 X High-Z Voltage on Ia, Ib, or Ic has exceeded Vth, which causes I LIM/DIS1 to go high. This internally disables Top and Bottom output FETs for ALL phases. X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs. X X X Pulled High X High-Z Pulling the I LIM/DIS1 pin high externally acts as a second disable input, which disables ALL output FETs. X X X Pulled Low 0 Determined by PWM inputs Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit function. The state of the outputs is strictly a function of the PWM inputs. X X X X X High-Z If V S is below the UVLO threshold all output FETs will be disabled. |
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