9

0735S–PLD–8/08

ATF22V10C(Q)

Figure 8-2.

I/O Diagram

9.

Power-down Mode

The ATF22V10C includes an optional pin-controlled power-down feature. When this mode is

enabled, the PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on

the PLCC package). When the PD pin is high, the device supply current is reduced to less than

100 mA. During power-down, all output data and internal logic states are latched and held.

Therefore, all registered and combinatorial output data remain valid. Any outputs that were in an

undetermined state at the onset of power-down will remain at the same state. During power-

down, all input signals except the power-down pin are blocked. Input and I/O hold latches

remain active to ensure that pins do not float to indeterminate levels, further reducing system

power. The power-down pin feature is enabled in the logic design file. Designs using the power-

down pin may not use the PD pin logic array input. However, all other PD pin macrocell

resources may still be used, including the buried feedback and foldback product term array

inputs.

PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the

JEDEC file. When the power-down feature is not specified in the design file, the IN/PD pin will be

configured as a regular logic input.

Note:

Some programmers list the 22V10 JEDEC compatible 22V10C (no PD used) separately from the

non-22V10 JEDEC compatible 22V10CEX (with PD used).