8

ATF1502AS(L)

0995K–PLD–6/05

Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the

PC. ISP is performed by using either a download cable, a comparable board tester or a simple

microprocessor interface.

When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins

must be reserved for the JTAG interface. However, the logic features that the macrocells have

associated with these I/O pins are still available to the design for burned logic functions.

To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector

Format (SVF) files can be created by Atmel-provided software utilities.

ATF1502AS devices can also be programmed using standard third-party programmers. With a

third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional

I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD applications for details.

ISP

Programming

Protection

The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O

from driving if the programming process is interrupted for any reason. The inputs and I/O

default to high-Z state during such a condition. In addition, the pin-keeper option preserves the

previous state of the input and I/O PMS during programming.

All ATF1502AS devices are initially shipped in the erased state, thereby making them ready to

use for ISP.

Note:

For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”

application note.

JTAG-BST/ISP

Overview

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the

ATF1502AS. The boundary-scan technique involves the inclusion of a shift-register stage

(contained in a boundary-scan cell) adjacent to each component so that signals at component

boundaries can be controlled and observed using scan testing methods. Each input pin and

I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The

ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is

automatically reset at power-up. T he five JT AG modes suppo rt ed include:

SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can

be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows

ATF1502AS programming to be described and implemented using any one of the third-party

development tools supporting this standard.

The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary-scan test-

ing (BST) and in-system programming (ISP) purposes. The ATF1502AS is programmable

through the four JTAG pins using the IEEE standard JTAG programming protocol established

by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for

in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is

not needed, then the four JTAG control pins are available as I/O pins.