4

2314E–FPSLI–6/05

AT94S Secure Family

2.

Internal Architecture

For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K FPSLIC

datasheet and the AT17 Series Configuration Memory datasheet, available on the Atmel web

site at http://www.atmel.com. This document only describes the differences between the AT94S

Secure FPSLIC and the AT94K FPSLIC.

3.

FPSLIC and Configurator Interface

• Fully In-System Programmable and Re-programmable

• When Security Bit Set:

– Data Verification Disabled

– Data Transfer to FPSLIC not Externally Visible

– Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip Erase

• When Security Bit Cleared:

– Entire Chip Erase Performed

– In-System Programming Enabled

– Data Verification Enabled

External Data pins allow for In-System Programming of the device and setting of the EEPROM-

based security bit. When the security bit is set (active) this programming connection will only

respond to a device erase command. Data cannot be read out of the external programming/data

pins when the security bit is set. The part can be re-programmed, but only after first being

erased.

4.

Programming and Configuration Timing Characteristics

Atmel’s Configurator Programming Software (CPS), available from the Atmel web site

(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the programming

algorithm for the embedded configurator; however, if you are planning to write your own soft-

ware or use other means to program the embedded configurator, the section below includes the

algorithm and other details.

4.1

The FPSLIC Configurator

The FPSLIC Configurator is a serial EEPROM memory which is used to load programmable

devices. This document describes the features needed to program the Configurator from within

its programming mode (i.e., when SER_EN is driven Low).

Reference schematics are supplied for ISP applications.

4.2

Serial Bus Overview

The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided by the

programmer, the second wire (cSDA) is a bi-directional signal and is used to provide data and

control information.

Information is transmitted on the serial bus in messages. Each MESSAGE is preceded by a

Start Condition and ends with a Stop Condition. The message consists of an integer number of

bytes, each byte consisting of 8 bits of data, followed by a ninth Acknowledge Bit. This Acknowl-

edge Bit is provided by the recipient of the transmitted byte. This is possible because devices