4

2322G–CNFG–03/06

AT17LV65A/128A/256A/512A/002A

3.

Device Description

The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface

directly with the FPGA device control signals. All FPGA devices can control the entire configura-

tion process and retrieve data from the configuration EEPROM without requiring an external

controller.

The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA

output pin and enable the address counter and the oscillator. When RESET/OE is driven Low,

the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin

also controls the output of the AT17A series configurator. If nCS is held High after the

RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is

driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE

is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regard-

less of the state of the nCS.

When the configurator has driven out all of its data and nCASC is driven Low, the device tri-

states the DATA pin to avoid contention with other configurators. Upon power-up, the address

counter is automatically reset.

This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,

this document will describe RESET/OE.

4.

Pin Description

Note:

1. The nCASC feature is not available on the AT17LV65A device.

Name

I/O

AT17LV65A/

AT17LV128A/

AT17LV256A

AT17LV512A/

AT17LV010A

AT17LV002A

20

PLCC

8

PDIP

20

PLCC

32

TQFP

20

PLCC

32

TQFP

DATA

I/O

2

1

2

31

2

31

DCLK

I

42

4242

WP1

I

––

5454

I

8

3

8787

nCS

I9

4

9

10

9

10

GND

10

5

10

12

10

12

nCASC

O

12

6

12151215

A2

I

READY

O

–

–

15

20

15

20

SER_EN

I

18

7

18

23

18

23

V

CC

20

8

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