8

2321I–CNFG–2/08

AT17LV65/128/256/512/010/002/040

4.10

A2

Device selection input, A2. This is used to enable (or select) the device during programming

(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.

4.11

READY

Open collector reset state indicator. Driven Low during power-up reset, released when power-up

is complete. It is recommended to use a 4.7 k

Ω pull-up resistor when this pin is used.

4.12

SER_EN

Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low

enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be

tied to V

4.13

V

CC

3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.

5.

FPGA Master Serial Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-

gram. The program is loaded either automatically upon power-up, or on command, depending

on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-

uration program from an external memory. The AT17LV Serial Configuration EEPROM has

been designed for compatibility with the Master Serial mode.

This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-

inx applications.

6.

Control of Configuration

Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and

self-explanatory.

• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.

• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.

• The CEO output of any AT17LV series configurator drives the CE input of the next

configurator in a cascaded chain of EEPROMs.

•SER_EN must be connected to V

• The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is

driven Low while the device is in its power-on reset cycle and released (tri-stated) when the

cycle is complete.

Note:

1. This pin is not available for the AT17LV65/128/256 devices.