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AT26F004-SSU Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT26F004-SSU Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 38 page 3 3588D–DFLASH–10/08 AT26F004 3. Block Diagram 4. Memory Array To provide the greatest flexibility, the memory array of the AT26F004 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations. The sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. Figure 2-1. 8-SOIC Top View Figure 2-2. 8-MLF Top View 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI CS SO WP GND VCC HOLD SCK SI 8 7 6 5 1 2 3 4 FLASH MEMORY ARRAY Y-GATING CONTROL LOGIC CS SCK SO SI HOLD WP Y-DECODER X-DECODER I/O BUFFERS AND LATCHES INTERFACE CONTROL AND LOGIC |
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