5

3590A–FLASH–12/05

AT49BV163D(T)

of the configuration register can be changed. Voltages applied to the RESET pin will not alter the

value of the configuration register. The value of the configuration register will affect the operation

of the I/O7 status bit as described below.

4.6.1

DATA Polling

The AT49BV163D(T) features Data Polling to indicate the end of a program cycle. If the status

configuration register is set to a “00”, during a program cycle an attempted read of the last

byte/word loaded will result in the complement of the loaded data on I/O7. Once the program

cycle has been completed, true data is valid on all outputs and the next cycle may begin. During

a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the

program or erase cycle has completed, true data will be read from the device. Data Polling may

begin at any time during the program cycle. Please see “Status Bit Table” on page 10 for more

details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has completed

a program or erase operation. Once I/O7 has gone high, status information on the other pins can

be checked.

The Data Polling status bit must be used in conjunction with the erase/program status bit as

shown in the algorithm in Figures 4-1 and and 4-2 on page 8.

4.6.2

Toggle Bit

In addition to Data Polling the AT49BV163D(T) provides another method for determining the end

of a program or erase cycle. During a program or erase operation, successive attempts to read

data from the memory will result in I/O6 toggling between one and zero. Once the program cycle

has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may

begin at any time during a program cycle. Please see “Status Bit Table” on page 10 for more

details.

The toggle bit status bit should be used in conjunction with the erase/program status bit as

shown in the algorithm in Figures 4-3 and and 4-4 on page 9.

4.6.3

Erase/Program Status Bit

The device offers a status bit on I/O5, which indicates whether the program or erase operation

has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable

to verify that an erase or a byte/word program operation has been successfully performed. If a

program (Sector Erase) command is issued to a protected sector, the protected sector will not

be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be

set high, indicating the program (erase) operation did not complete as requested. Once the

erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-

mand to return to the read mode. The erase/program status bit is a “0” while the erase or

program operation is still in progress. Please see “Status Bit Table” on page 10 for more details.

4.7

Sector Lockdown

Each sector has a programming lockdown feature. This feature prevents programming of data in

the designated sectors once the feature has been enabled. These sectors can contain secure

code that is used to bring up the system. Enabling the lockdown feature will allow the boot code

to stay in the device while data in the rest of the device is updated. This feature does not have to

be activated; any sector’s usage as a write-protected region is optional to the user.