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AT25DF041A-MH-Y Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT25DF041A-MH-Y Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 41 page 4 3668D–DFLASH–9/08 AT25DF041A 3. Block Diagram 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations. The sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break- down of each physical sector. FLASH MEMORY ARRAY Y-GATING CS SCK SO SI Y-DECODER X-DECODER I/O BUFFERS AND LATCHES CONTROL AND PROTECTION LOGIC SRAM DATA BUFFER WP INTERFACE CONTROL AND LOGIC |
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