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AT89LP216-20PU Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT89LP216-20PU Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 96 page  5 3621C–MICRO–6/08 AT89LP216 5.3 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts. 5.4 Timer/Counters By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the prescaler (Table 9-2 on page 13). Setting TPS = 1011B will cause the timers to count once every 12 clocks. The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function. 5.5 Serial Port The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock fre- quency in the standard 8051; and output data is only stable around the rising edge of the serial clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP216 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates. 5.6 Watchdog Timer The Watchdog Timer in AT89LP216 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the counting rate. 5.7 I/O Ports The I/O ports of the AT89LP216 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also con- figure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse. When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be weakly pulled high. 5.8 Reset The RST pin of the AT89LP216 is active-low as compared with the active high reset in the stan- dard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset. |
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