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AT83C5103XXX-ICRIL Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT83C5103XXX-ICRIL Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 64 page 8 4134D–8051–02/08 Registers Table 1. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = XX0X X000b 7 6 5 4 3 2 1 0 PCAX2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7 – Reserved The value read from this bit is indeterminate. Do not set this bit. 6 – Reserved The value read from this bit is indeterminate. Do not set this bit. 5 PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4 – Reserved The value read from this bit is indeterminate. Do not set this bit. 3 – Reserved The value read from this bit is indeterminate. Do not set this bit. 2 T1X2 Timer1 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1 T0X2 Timer0 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0 X2 CPU Clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals "X2" bits. |
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