AT61162E-PM40M-E datasheet(8/14 Pages) ATMEL

Part #	AT61162E-PM40M-E

Description	Rad Hard 2-Mbit x 8 SRAM Cube

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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8 / 14 page

8

4157E–AERO–07/05

AT61162E

Data Retention

Mode

Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup-

ply current are guaranteed over temperature. The following rules ensure data retention:

1.

During data retention CS must be held high within V

CC to VCC -0.2V or, chip select BS

must be held down within GND to GND +0.2V.

2.

Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-

mizing power dissipation.

3.

During power up and power down transitions CS and OE must be kept between V

CC +

0.3V and 70% of V

CC, or with BS between GND and GND -0.3V.

4.

The RAM can begin operation > TR ns after V

CC reaches the minimum operation voltages

(3V).

Timing

Data Retention Characteristics

Notes:

1. T

AVAV = Read Cycle Time

2. All CS = V

CC or All BS = CS = GND, VIN = Gnd/VCC.

3V

BS

Parameter

Description

Min

Typical TA = 25°CMax

Unit

V

CCDR

VCC for data

retention

2.0

–

V

tCDR

Chip deselect to

data retention time

0.0

–

ns

t

R

Operation recovery

time

t

AVAV

(1)

––

ns

I

CCDR1

(2)

Data retention

current at 2.0V

–0.040

12

mA

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AT61162E-PM40M-E Datasheet(PDF) 8 Page - ATMEL Corporation

AT61162E-PM40M-E Datasheet(HTML) 8 Page - ATMEL Corporation

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