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KAD5512HP-17Q72 Datasheet(PDF) 7 Page - Intersil Corporation |
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KAD5512HP-17Q72 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 30 page  7 FN6808.0 December 5, 2008 ESD Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Intersil for the specific ESD sensitivity rating of this product. Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS ADC OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 60 fs Output Clock to Data Propagation Delay, LVDS Mode DDR Rising Edge tDC -260 -50 120 ps DDR Falling Edge tDC -160 10 230 ps SDR Falling Edge tDC -260 -40 230 ps Output Clock to Data Propagation Delay, CMOS Mode DDR Rising Edge tDC -220 -10 200 ps DDR Falling Edge tDC -310 -90 110 ps SDR Falling Edge tDC -310 -50 200 ps Latency (Pipeline Delay) L 8.5 cycles Overvoltage Recovery tOVR 1cycles SPI INTERFACE (Notes 6, 7) SCLK Period Write Operation t CLK 64 ns Read Operation tCLK 264 ns SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write 25 50 75 % SCLK ↑ to CSB↓ Setup Time Read or Write tS -4 ns SCLK ↑ to CSB↑ Hold Time Read or Write tH -12 ns SCLK ↑ to Data Setup Time Read or Write tDS -4 ns SCLK ↑ to Data Hold Time Read or Write tDH -12 ns NOTES: 6. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 7. The SPI may operate asynchronously with respect to the ADC sample clock. Thermal Impedance PARAMETER SYMBOL 48 LD QFN TYP 72 LD QFN TYP UNIT Junction to Ambient (Note 8) θJ A 35 27 °C/W NOTE: 8. Paddle soldered to ground plane. KAD5512HP |
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