KAD5610P-17Q72 datasheet(6/27 Pages) INTERSIL

Part #	KAD5610P-17Q72

Description	Dual 10-Bit, 250/210/170/125MSPS A/D Converter

Download	27 Pages

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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6 / 27 page

6

FN6810.1

January 30, 2009

Digital Specifications

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

INPUTS

Input Current High (SDIO,RESETN)

IIH

VIN = 1.8V

0

1

10

µA

Input Current Low (SDIO,RESETN)

IIL

VIN = 0V

-25

-12

-5

µA

Input Voltage High (SDIO, RESETN)

VIH

1.17

V

Input Voltage Low (SDIO, RESETN)

VIL

.63

V

Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT)

(Note 6)

IIH

15

25

40

µA

Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT)

IIL

-40

25

-15

µA

Input Capacitance

CDI

3pF

LVDS OUTPUTS

Differential Output Voltage

VT

3mA Mode

620

mVP-P

Output Offset Voltage

VOS

3mA Mode

950

965

980

mV

Output Rise Time

tR

500

ps

Output Fall Time

tF

500

ps

CMOS OUTPUTS

Voltage Output High

VOH

IOH = -500µA

OVDD - 0.3

OVDD - 0.1

V

Voltage Output Low

VOL

IOL = 1mA

0.1

0.3

V

Output Rise Time

tR

1.8

ns

Output Fall Time

tF

1.4

ns

Timing Diagrams

FIGURE 1. LVDS TIMING DIAGRAM (DDR)

FIGURE 2. CMOS TIMING DIAGRAM (DDR)

LATENCY = L CYCLES

tDC

tPD

tA

SAMPLE N

tCPD

INP

INN

CLKN

CLKP

CLKOUTN

CLKOUTP

D[9:0]P

D[9:0]N

A DATA

N-L + 1

A DATA

N-L

B DATA

N-L

B DATA

N-L + 1

A DATA

N-L + 2

B DATA

N-L + 2

A DATA

N

LATENCY = L CYCLES

tDC

tPD

tA

SAMPLE N

tCPD

INP

INN

CLKN

CLKP

CLKOUT

D[9:0]

A DATA

N-L + 1

A DATA

N-L

B DATA

N-L

B DATA

N-L + 1

A DATA

N-L + 2

B DATA

N-L + 2

A DATA

N

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KAD5610P-17Q72 Datasheet(PDF) 6 Page - Intersil Corporation

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