8

M67206H

4143J–AERO–04/07

Bi-directional Mode

Applications which require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M67206H as shown

in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each

system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow – Through

Modes

Two types of flow-through modes are permitted: a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 17) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag); how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On toggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow-through mode (Figure 18), the FIFO stack allows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

Figure 4. Block Diagram of 49152 bits × 9 FIFO Memory (Depth Expansion)

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