3

AT28C010-12DK

4259C–AERO–05/05

Device Operation

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READ: The AT28C010-12DK is accessed like a Static RAM. When CE and OE are

low and WE is high, the data stored at the memory location determined by the

address pins is asserted on the outputs. The outputs are put in the high impedance

state when either CE or OE is high. This dual-line control gives designers flexibility

in preventing bus contention in their system.

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BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively)

and OE high initiates a write cycle. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is latched by the first rising edge of CE or

WE. Once a byte write has been started it will automatically time itself to completion.

Once a programming operation has been initiated and for the duration of t

operation will effectively be a polling operation.

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PAGE WRITE: The page write operation of the AT28C010-12DK allows 1 to 128

bytes of data to be written into the device during a single internal programming

period. A page write operation is initiated in the same manner as a byte write; the

first byte written can then be followed by 1 to 127 additional bytes. Each successive

byte must be written within 150

µs (t

exceeded the AT28C010-12DK will cease accepting data and commence the

internal programming operation. All bytes during a page write operation must reside

on the same page as defined by the state of the A7 - A16 inputs. For each WE high

to low transition during the page write operation, A7 - A16 must be the same.

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The A0 to A6 inputs are used to specify which bytes within the page are to be

written. The bytes may be loaded in any order and may be altered within the same

load period. Only bytes which are specified for writing will be written; unnecessary

cycling of other bytes within the page does not occur.

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DATA POLLING: The AT28C010-12DK features DATA Polling to indicate the end of

a write cycle. During a byte or page write cycle an attempted read of the last byte

written will result in the complement of the written data to be presented on I/O7.

Once the write cycle has been completed, true data is valid on all outputs, and the

next write cycle may begin. DATA Polling may begin at anytime during the write

cycle.

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TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another

method for determining the end of a write cycle. During the write operation,

successive attempts to read data from the device will result in I/O6 toggling between

one and zero. Once the write has completed, I/O6 will stop toggling and valid data

will be read. Reading the toggle bit may begin at any time during the write cycle.

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DATA PROTECTION: If precautions are not taken, inadvertent writes may occur

during transitions of the host system power supply. Atmel has incorporated both

hardware and software features that will protect the memory against inadvertent

writes.

For more information see the application note:

http://www.atmel.com/dyn/resources/prod_documents/DOC0544.PDF

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HARDWARE PROTECTION: Hardware features protect against inadvertent writes

reached 3.8V the device will automatically time out 5 ms (typical) before allowing a

write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write

cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs

will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled data protection feature

has been implemented on the AT28C010-12DK. When enabled, the software data

protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled