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EP1AGX50CF780C6N Datasheet(PDF) 11 Page - Altera Corporation |
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EP1AGX50CF780C6N Datasheet(HTML) 11 Page - Altera Corporation |
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11 / 296 page  Altera Corporation 2–3 May 2008 Arria GX Device Handbook, Volume 1 Arria GX Architecture Figure 2–2 shows functional blocks that make up a transceiver channel. Figure 2–2. Arria GX Transceiver Channel Block Diagram Notes to Figure 2–2: (1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA. n = 8 or 10. (2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20. Each transceiver channel is full-duplex and consists of a transmitter channel and a receiver channel. The transmitter channel contains the following sub-blocks: ■ Transmitter phase compensation first-in first-out (FIFO) buffer ■ Byte serializer (optional) ■ 8B/10B encoder (optional) ■ Serializer (parallel-to-serial converter) ■ Transmitter differential output buffer The receiver channel contains the following: ■ Receiver differential input buffer ■ Receiver lock detector and run length checker ■ Clock recovery unit (CRU) ■ Deserializer ■ Pattern detector ■ Word aligner ■ Lane deskew ■ Rate matcher (optional) ■ 8B/10B decoder (optional) ■ Byte deserializer (optional) ■ Receiver phase compensation FIFO buffer Deserializer Serializer Word Aligner 8B/10B Decoder XAUI Lane Deskew Byte Deserializer 8B/10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Byte Serializer Phase Compensation FIFO Buffer Rate Matcher PCS Digital Section FPGA Fabric PMA Analog Section Receiver PLL Transmitter PLL Clock Recovery Unit m n n m (1) (2) (2) (1) |
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