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EP1AGX60DF1152C6N Datasheet(PDF) 5 Page - Altera Corporation |
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EP1AGX60DF1152C6N Datasheet(HTML) 5 Page - Altera Corporation |
5 / 296 page Altera Corporation 1–3 May 2008 Arria GX Device Handbook, Volume 1 Features Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration Source- synchronous receive channels 31 31 31 31 31, 42 31 31 42 47 Source- synchronous transmit channels 29 29 29 29 29, 42 29 29 42 45 M512 RAM blocks (32 × 18 bits) 166 197 313 326 478 M4K RAM blocks (128 × 36 bits) 118 140 242 252 400 M-RAM blocks (4096 × 144 bits) 11 2 2 4 Total RAM bits 1,229,184 1,348,416 2,475,072 2,528,640 4,477,824 Embedded multipliers (18 × 18) 40 56 104 128 176 DSP blocks 10 14 26 32 44 PLLs 4 4 4 4, 8 4 8 8 Maximum user I/O pins 230, 341 230 341 229 350, 514 229 350 514 538 Table 1–1. Arria GX Device Features (Part 2 of 2) Feature EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E CC D C D C D E E |
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