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ATAM893-D Datasheet(PDF) 4 Page - ATMEL Corporation |
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ATAM893-D Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 98 page 4 4680C–4BMCU–01/05 ATAM893-D 3.5 RC-oscillator Frequency The typical frequency of the internal RC-oscillator is about 5% higher for the Flash part com- pared to the ROM part. But due to the wide range of ±50% overall tolerances this should not affect the application too much. This 5% is also valid for the RC-oscillator with an external resistor. For a frequency of 4 MHz the flash part requires a resistor of 180 k, while the ROM part only needs 170 k. 3.6 High Drive Outputs On request the ROM parts offer a high current output selection. These pins than are twice as strong as in the standard configuration. The ATAM893-D does not offer this selection. Only the Timer 2 output (BP42) and the Timer 3 output (BP60) are configured as high current outputs for the low side driver by default. This configuration is fixed and cannot be changed by the customer. 4. MARC4 Architecture 4.1 General Description The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals. The CPU is based on the Harvard architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both, an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 4-1. MARC4 Core Instruction decoder CCR TOS ALU RAM RP X Y Program 256 x 4-bit MARC4 CORE Clock Reset Sleep Memory bus I/O bus Instruction bus Reset System clock Interrupt controller On-chip peripheral modules memory SP PC |
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