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ATAR890X-YYY-TKSYZ Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATAR890X-YYY-TKSYZ Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 75 page  8 ATAR090/ATAR890 4696D–4BMCU–12/04 An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt ser- vice routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the cor- responding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt ser- vice routine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core). Figure 8. Interrupt Handling 7 6 5 4 3 2 1 0 INT5 active INT7 active INT2 pending SWI0 INT2 active INT0 pending INT0 active INT2 RTI RTI INT5 INT3 active INT3 RTI RTI RTI INT7 Time Main/ Autosleep Main/ Autosleep RTI |
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