ACS8515 datasheet(11/50 Pages) SEMTECH

Part #	ACS8515

Description	Line Card Protection Switch for SONET or SDH Network Elements

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Manufacturer	SEMTECH [Semtech Corporation]

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11 / 50 page

Revision 2.01/December 2005

Semtech Corp.

www.semtech.com

11

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS

FINAL

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The registers sts_curr_inc_offset (address 0C,

0D, 07) report the frequency of the DPLL with

respect to the external TCXO frequency. This is

a 19 bit signed number with one LSB

representing 0.0003 ppm (range of +/- 80

ppm). Reading this regularly can show how the

currently locked source is varying in value e.g.

due to wander on its input.

The ACS8515 performs automatic frequency

monitoring with an acceptable input frequency

offset range of +/- 16.6 ppm. The ACS8515

DPLL has a programmable frequency limit of

+/- 80 ppm. If the range is programmed to be

> 16.6 ppm, the frequency monitors should be

disabled so the input reference source is not

automatically rejected as out of frequency

range.

Output Clock Ports

The ACS8515 supports two SEC output clocks,

on TTL and PECL/LVDS ports, and a pair of

secondary output clocks, ‘Frame-Sync’ and

‘Multi-Frame-Sync’. The two output clocks are

individually controllable. The ‘Frame-Sync’ and

‘Multi-Frame-Sync’ are derived from the main

SEC clock. The frequencies of the output clock

are selectable from a range of pre-defined spot

frequencies, with a variety of output

technologies supported, as defined in Table 8.

Low Speed Output Clock

The O2 SEC clock is supplied on a TTL port with

a fixed frequency of 19.44 MHz.

Table 6. Amplitude and Frequency values for Jitter Tolerance

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)

(for inputs supporting G.783 compliant sources)

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