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ACS8520 Datasheet(PDF) 11 Page - Semtech Corporation |
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ACS8520 Datasheet(HTML) 11 Page - Semtech Corporation |
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11 / 150 page  ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3.02/October 2005 © Semtech Corp. Page 11 www.semtech.com ACS8520 SETS frequency to 8 kHz, the post-division frequency. (XX = “Leaky Bucket” ID for this input). (ii) To achieve 8 kHz, the 10 MHz input must be divided by 1,250. So, if DivN, = 250 = (N+1) then N must be set to 1,249. This is done by writing 4E1 hex (1,249 decimal) to the DivN register pair Reg. 46/47. Direct Lock Mode 155 MHz. The max frequency allowed for phase comparison is 77.76MHz, so for the special case of a 155 MHz input set to Direct Lock Mode, there is a divide-by-two function automatically selected to bring the frequency down to within the limits of operation. PECL/LVDS/AMI Input Port Selection The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL differential inputs should be fixed with one input High (VDD) and the other input Low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled High and the other Low. An AMI port supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703[6]. Departures from the nominal pattern are detected within the ACS8520, and may cause reference-switching if too frequent. See section DC Characteristics: AMI Input/Output Port, for more details. If the AMI port is unused, the pins (I1 and I2) should be tied to GND. Table 4 Input Reference Source Selection and Priority Table Port Number Channel Number (Bin) Input Port Technology Frequencies Supported Default Priority I1 0001 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 2 I2 0010 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 3 I3 0011 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 4 I4 0100 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 5 I5 0101 LVDS/PECL LVDS default Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 6 I6 0110 PECL/LVDS PECL default Up to 155.52 MHz (see Note (ii)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 7 I7 0111 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 8 I8 1000 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 9 I9 1001 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 10 I10 1010 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 11 I11 1011 TTL/CMOS Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default (Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz 12/1 (Note (iii)) I12 1100 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 13 |
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