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ACS8525T Datasheet(PDF) 6 Page - Semtech Corporation |
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ACS8525T Datasheet(HTML) 6 Page - Semtech Corporation |
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6 / 112 page  ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3.01/August 2005 © Semtech Corp. Page 6 www.semtech.com ACS8525 LC/P 17 FrSync O TTL/CMOS Output Reference: 8 kHz Frame Sync output. 18 MFrSync O TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync output. 19, 20 O1POS, O1NEG O LVDS/PECL Output Reference: Programmable, default 38.88 MHz, LVDS. 23, 24 SEC1_POS, SEC1_NEG I PECL/LVDS Input Reference: Programmable, default 19.44 MHz, PECL. 25, 26 SEC2_POS, SEC2_NEG I PECL/LVDS Input Reference: Programmable, default 19.44 MHz PECL. 28 SYNC1 I TTLD (Master) Multi-Frame Sync 2kHz Input: Connect to 2 or 8 kHz Multi-Frame Sync output of Master SETS. 29 SEC1 I TTLD (Master) Input Reference: Programmable, default 8 kHz. 30 SEC2 I TTLD (Slave) Input Reference: Programmable, default 8 kHz. 33 SYNC2 I TTLD (Slave) Multi-Frame Sync 2 kHz: Connect to 2 or 8 kHz Multi-Frame Sync output of Slave SETS. 34 SEC3 I TTLD (Stand-by) Input Reference: External stand-by reference clock source, programmable, default 19.44MHz. 35 SYNC3 I TTLD (Stand-by) Input Reference: External stand-by 2 or 8 kHz Multi-Frame Sync clock source. 37 TRST I TTLD JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 is Boundary Scan stand-by mode, still allowing normal device operation (JTAG logic transparent). NC if not used. 41 TMS I TTLD JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. NC if not used. 42 CLKE I TTLD SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of SCLK to be active. 43 SDI I TTLD Serial Interface Address: Serial Data Input. 44 CSB I TTLU Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface. 47 SCLK I TTLD Serial Data Clock. When this pin goes High data is latched from SDI pin. 48 PORB I TTLU Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. 49 TCK I TTLD JTAG Clock: Boundary Scan clock input. 50 TDO O TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK. 51 TDI I TTLD JTAG Input: Serial test data Input. Sampled on rising edge of TCK. 52 SDO O TTLD Interface Address: SPI compatible Serial Data Output. 56 O2 O TTL/CMOS Output Reference: Programmable, default 19.44 MHz. 64 SONSDHB I TTLD SONET or SDH Frequency Select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. Table 3 Other Pins (cont...) Pin Number Symbol I/O Type Description |
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