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ACS8946T Datasheet(PDF) 5 Page - Semtech Corporation |
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ACS8946T Datasheet(HTML) 5 Page - Semtech Corporation |
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5 / 40 page  ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3/November 2006 © Semtech Corp. Page 5 www.semtech.com ACS8946 JAM PLL 15 CFG_OUT2 O LVTTL/ LVCMOS Configuration pin, used in the configuration on power-up of expected input clock frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[0:7] pins as required. See “Configuration” on page 13. 16 ALARMC_CO3 O LVTTL/ LVCMOS Activity alarm output for the currently selected input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up, where it is used as a configuration output pin that may be connected to CFG_IN[0:7] input pins as required. See “Configuration” on page 13. 17 LOCKB O Analog Lock detect output. This is a pulse-width modulated output current, with each pulse typically +10 µA. The output produces a pulse with a width in proportion to the phase error seen at the internal phase detector. This pin should be connected via an external parallel capacitor and resistor to ground. The pin voltage will then give an indication of phase lock: When low, the device is phase locked; when high the device has frequent large phase errors and so is not phase locked. The value of the RC components used determines the time and level of consistency required for lock indication. If LOCKB is disabled by configuration the LOCKB output is held low. 18 CFG_IN0 I LVTTL/ LVCMOSD Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 19 to set the available output rates as shown in Table 11. 19 CFG_IN1 I LVTTL/ LVCMOSD Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 18 to set the available output rates as shown in Table 11. 20 CFG_IN2 I LVTTL/ LVCMOSD Schmitt Trigger Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 21 to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1 and OUT2 as in Table 10. 21 CFG_IN3 I LVTTL/ LVCMOSD Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 20 to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1 and OUT2 as in Table 10. 22 CFG_IN4 I LVTTL/ LVCMOSD Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 23 to set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins 8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12. 23 CFG_IN5 I LVTTL/ LVCMOSD Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 22 to set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins 8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12. Table 3 Functional Pins (cont...) Pin No. Symbol I/O Type Description |
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