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T6817-TKSY Datasheet(PDF) 9 Page - ATMEL Corporation |
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T6817-TKSY Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 16 page 9 4670D–BCD–04/07 T6817 4 Thermal Prewarning and Shutdown 4.1 Thermal prewarning TjPWset 125 145 165 °C A 4.2 Thermal prewarning TjPWreset 105 125 145 °C A 4.3 Thermal prewarning hysteresis ∆T jPW 320 K A 4.4 Thermal shutdown T j switch off 150 170 190 °C A 4.5 Thermal shutdown T j switch on 130 150 170 °C A 4.6 Thermal shutdown hysteresis ∆T j switch off 320 K A 4.7 Ratio thermal shutdown/thermal prewarning T j switch off/ T jPW set 1.05 1.17 A 4.8 Ratio thermal shutdown/thermal prewarning Tj switch on/ T jPW reset 1.05 1.2 A 5 Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < VOV 5.1 On resistance I Out = 600 mA 8, 15, 17 R DS OnL 1.5 Ω A 5.2 On resistance IOut = –600 mA 12, 14, 16 RDS OnH 2.0 Ω A 5.3 Output clamping voltage I LS1-3 = 50 mA 8, 15, 17 V LS1-3 40 60 V A 5.4 Output leakage current VLS1–3 = 40V all output stages off 8, 15, 17 ILS1–3 10 µA A 5.5 Output leakage current VHS1-3 = 0V all output stages off 2, 3, 12, 13, 15, 28 IHS1–3 –10 µA A 5.7 Inductive shutdown energy 8, 12, 14 to 17 W outx 15 mJ D 5.8 Output voltage edge steepness 8, 12, 14 to 17 dV LS1–3/dt dVHS1–3/dt 50 200 400 mV/µs A 5.9 Overcurrent limitation and shutdown threshold 8, 15, 17 ILS1–3 650 950 1250 mA A 5.10 Overcurrent limitation and shutdown threshold 12, 14, 16 I HS1–3 –1250 –950 –650 mA A 5.11 Overcurrent shutdown delay time Input register bit 14 (SCT) = high bit 14 (SCT) = low tdSd t dSd 70 8.75 100 140 17.5 ms ms A A 5.12 Open load detection current Input register bit 13 (OLD) = low, output off 8, 15, 17 I LS1–3 60 200 µA A 8. Electrical Characteristics (Continued) 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level |
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