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ATA6828-T2SY Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATA6828-T2SY Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 16 page 9 4530G–BCD–09/05 T6818/ATA6828 3.6 Thermal shutdown hysteresis ∆T j switch off 15 ° CB 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ T jPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset T j switch on/ TjPW reset 1.05 1.2 B 4 Output Specification (OUT1-OUT3) 4.1 On resistance I Out 1-3 = –1.3 A 2, 12, 13 R DSOn1-3 1.1 Ω A 4.2 I Out 1-3 = 1.3 A 2, 12, 13 R DSOn1-3 1.1 Ω A 4.3 High-side output leakage current V Out 1-3 = 0 V, output stages off 2, 12, 13 IOut1-3 –15 µA A 4.4 Low-side output leakage current V Out 1-3 = VVS, output stages off 2, 12, 13 I Out1-3 200 µA A 4.5 High-side switch reverse diode forward voltage I Out 1-3 = 1.5 A 2, 12, 13 V Out1-3 – VVS 1.5 V A 4.6 Low-side switch reverse diode forward voltage I Out 1-3 = –1.5 A 2, 12, 13 V Out 1-3 –1.5 V A 4.7 High-side overcurrent limitation and shutdown threshold 2, 12, 13 I Out1-3 –2.5 –2 –1.5 A A 4.8 Low-side overcurrent limitation and shutdown threshold 2, 12, 13 IOut1-3 1.5 2 2.5 A A 4.9 Overcurrent shutdown delay time tdSd 10 40 µs A 4.10 High-side open-load detection threshold 2, 12, 13 I Out1-3 –45 –30 –15 mA A 4.11 Low-side open-load detection threshold 2, 12, 13 IOut1-3 15 30 45 mA A 4.12 Open-load detection delay time tdSd 200 600 µs A 4.13 High-side output switch on delay(1) VVS = 13 V RLoad = 30 Ω t don 20 µs A 4.14 Low-side output switch on delay(1) VVS = 13 V R Load = 30 Ω tdon 20 µs A 4.15 High-side output switch off delay(1) V VS = 13 V RLoad = 30 Ω t doff 20 µs A 8. Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; –40°C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms |
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