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SC471 Datasheet(PDF) 9 Page - Semtech Corporation |
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SC471 Datasheet(HTML) 9 Page - Semtech Corporation |
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9 / 27 page  9 © 2008 Semtech Corp. SC471/SC471A www.semtech.com POWER MANAGEMENT Applications Information SC471/A Synchronous Buck Controller The SC471/A is a synchronous power supply controller which simplifies the task of designing a multi-level power supply suitable for controlling video chip sets and other multi-voltage circuits. The SC471/A provides two inputs (G0/G1) which control internal pull-down transistors used to select up to four adjustable output voltages. Battery and +5V Bias Supplies The SC471/A requires an external +5V bias supply in addition to the VBAT supply. If stand-alone capability is required, the +5V bias supply can be generated with an external linear regulator. Pseudo-Fixed-Frequency Constant On-Time PWM Controller The PWM control method is a constant-on-time, pseudo- fixed-frequency PWM controller, see Figure 1. The ripple voltage seen across the output capacitor’s ESR provides the PWM ramp signal, eliminating the need for a current sense resistor. The on-time is determined by an internal one-shot whose period is proportional to output voltage, and inversely proportional to input voltage. A separate one-shot sets the minimum off-time (typically 350ns). Q1 Q2 L COUT VBAT ESR + CIN VOUT FB Threshold 0.75V VFB VLX VLX TON FB R1 R2 Figure 1 On-Time One-Shot (TON) The internal on-time one-shot comparator has two inputs. One input senses output voltage via the VOUT pin, while the other input samples VBAT via the LX pin and creates a proportional current which charges an internal capaci- tor. The TON time is the time required for this capacitor to charge from zero volts to VOUT, thereby making TON directly proportional to output voltage and inversely pro- portional to input voltage. This implementation results in a fairly constant switching frequency without the need of a clock generator. The internal frequency is optimized for 325kHz. The general equation for the on-time is: TON (nsec) = 2560 • (VOUT/VBAT) + 35 FREQ NOM (kHz) = 10 6 • VOUT/(2560 • VOUT + 35 • VBAT) Immediately after the DH on-time, the DL output drives high to energize the low-side MOSFET. DL has a minimum high time of typically 350nsec, after which DL will continue to stay high until one of the following occur: FB drops to the 0.75V reference The Zero Cross detector trips if power save is active The Negative Current Limit detector trips The Zero Cross detector monitors the voltage across the low-side MOSFET and trips when it reaches zero. If this oc- curs on eight consecutive cycles, then DL will subsequently shut off when the Zero Cross detector trips. See the PSAVE Operation section. Both MOSFETS will then stay off until FB drops to 0.75V, which will begin the next DH on-time. This is normal operation at light load. The Negative Current Limit detector trips when the drain voltage at the low-side MOSFET reaches typically +80mV, indicating a large negative current is being drawn through the inductor from VOUT. When this occurs, DL drives low. Both MOSFETS will then stay off until FB drops to 0.75V, which will begin the next DH on-time. Tripping the Negative Current detector is rare. If DL drives low because FB has dropped to the 0.75V refer- ence, then another DH on-time is started: this is normal operation at heavy load. If DL drives low because of the • • • |
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