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U9280M-H-XXXZ-FSG3Y Datasheet(PDF) 11 Page - ATMEL Corporation

Part # U9280M-H-XXXZ-FSG3Y
Description  Microcontroller with Transponder Interface
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

U9280M-H-XXXZ-FSG3Y Datasheet(HTML) 11 Page - ATMEL Corporation

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11
4591B–RFID–09/05
U9280M-H
3.9.2
Control Byte Format
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control
bits and the read/not write-bit.
3.9.3
Data Transfer Sequence
• Before the START condition and after the STOP condition the device is in standby mode and
the SDA-line is switched to input with a pull-up resistor.
• The START condition follows a control byte that determines the following operation. Bit 0 of
the control byte is used to control the following transfer direction. A 0 defines a write access
and a 1 a read access.
3.10
EEPROM
The EEPROM has a size of 512 bits and is organized as a 32
× 16-bit matrix. To read and write
data to and from the EEPROM the serial interface must be used. The interface supports one and
two byte write accesses and one to n-byte read accesses to the EEPROM.
3.10.1
Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte contains
the row address, the mode control bits and the read/write bit that is used to control the direction
of the following transfer. A 0 defines a write access and a 1 a read access. The five address bits
select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the com-
plete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or
overwritten via the serial interface. The two mode control bits C1 and C2 define in which order
the accesses to the buffer are performed: High byte – low byte or low byte – high byte. The
EEPROM also supports autoincrement and autodecrement read operations. After sending the
start address with the corresponding mode, consecutive memory cells can be read row by row
without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with a 0 or with a 1.
3.10.2
Write Operations
The EEPROM allows 8-bit and 16-bit write operations. A write access starts with the START
condition followed by a write control byte and one or two data bytes from the master. It is com-
pleted via the STOP condition from the master after the acknowledge cycle.
If the EEPROM receives the control byte, it loads the content of the addressed memory cell into
a 16-bit read/write buffer. After the first data byte has been received the EEPROM starts the
internal programming cycle. It consists of an erase cycle (write “zeros”) and the write cycle (write
“ones”). Each cycle takes about 10 ms. The write cycle is started after the stop condition and the
complete buffer is stored back automatically to the EEPROM. That means for two-byte write
operations, the second byte must be transferred within the erase cycle otherwise only the first
byte will be stored in the EEPROM and the second byte will be ignored.
EEPROM address
Mode control bits
Read/Write
Start
A4
A3
A2A1A0
C1
C0
R/W
Ackn
Start
Control byte
Ackn.
Data byte
Ackn.
Data byte
Ackn.
Stop


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