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2

XE1209

Ultra Low Power CMOS Transceiver

1

PIN DESCRIPTION

Pin #

Name

Description

1

TEST

Test pin

2

VSS

Ground for digital

3

QIN

Xtal pin or input for external clock

4

VDDA

Supply voltage for analog

5

QOUT

Xtal pin

6

VSSA

Ground for analog

7

IREF

Iref node for external resistance

8

VREF

Vref node for external capacitance

9

SUPTEST

Test pin

10

RE

Receiver enable

11

INA

RF input signal

12

INB

RF input signal

13

VSSPA

Ground for RF power amplifier

14

PAOUT

RF power amplifier output

15

VDD

Supply voltage for digital

16

DCLK

Received data clock output

17

DATA

Input/output bit stream or output of the carrier detector

18

DE

Data enable for 3-wire communication

19

SD

Data input for 3-wire communication

20

SC

Clock input for 3-wire communication

2

TYPICAL APPLICATION

The product is to be used in a system for low frequency RF data communications. The transmission is made with 2-

level CPFSK modulation. The modulated signal has a carrier frequency fc and a deviation frequency ∆f; the coding of

the data is the following:

above shows the structure of the transceiver and the external components required by the application. A 3-wire

bus allows the product to receive configuration data from a microcontroller. Note: pin TEST remains

unconnected.

2.1

TYPICAL EXTERNAL COMPONENTS

Besides the components needed for the RF communication itself, the following external components are required:

Name

Type

Pins to be connected

Value

Tolerance

Max. Temp. variation

Cvdd

Capacitor

VDD - VSS

100 nF

± 10 %

± 5 % over -10 °C to 60 °C

Cvref

Capacitor

VREF - VSS

47 nF

± 10 %

± 5 % over -10 °C to 60 °C

Riref

Resistance

IREF - VSS

280 k

Ω

± 1 %

± 100 ppm/K

Xtal

Crystal

QIN - QOUT

32.768 kHz

± 20 ppm

- 50 ppm over -10 to 60 °C

The reference of the crystal used for Xtal is the following:

“DS26 watch crystal” from Micro Crystal Switzerland

3

GENERAL FUNCTIONAL DESCRIPTION

The XE1209 is composed of 6 main functional blocks:

Receiver

The receiver channel converts a 2-level CPFSK modulated signal into a bit stream. It is composed of the following

blocks: preamplifier, down-converters (0-IF architecture), channel filters, limiters, demodulator, and bit

synchronizer.