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ATA556711N-DDT1 Datasheet(PDF) 3 Page - ATMEL Corporation |
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ATA556711N-DDT1 Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 36 page 3 4874F–RFID–07/08 ATA5567 3.2 Data-rate Generator The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50, RF/64, RF/100, and RF/128). 3.3 Write Decoder This function decodes the write gaps and verifies the validity of the data stream according to the Atmel e555x write method (pulse interval encoding). 3.4 HV Generator This on-chip charge pump circuit generates the high voltage required for programming of the EEPROM. 3.5 DC Supply Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu- lates this RF source and uses it to generate its supply voltage. 3.6 Power-On Reset (POR) This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached. 3.7 Clock Extraction The clock extraction circuit uses the external RF signal as its internal clock source. 3.8 Controller The control-logic module executes the following functions: • Loads mode register with configuration data from EEPROM block 0 after power-on and also during reading • Controls memory access (read, write) • Handles write data transmission and write error modes The first two bits of the reader to tag data stream are the opcode, for example, write, direct access, or reset. In password mode, the 32 bits received after the opcode are compared with the password stored in memory block 7. 3.9 Mode Register The mode register stores the configuration data from the EEPROM block 0. It is continually refreshed at the start of every block read and (re-)loaded after any POR event or reset com- mand. On delivery, the mode register is preprogrammed with the value 0014 8000h which corresponds to continuous read of block 0, Manchester coded, RF/64. |
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