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ATA5760N-TGQY Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATA5760N-TGQY Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 41 page  9 4896D–RKE–08/08 ATA5760/ATA5761 6. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and trans- fers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called poll- ing mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcon- troller or it can be operated by up to five uni-directional ports. 7. Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle T Clk is derived from the crystal oscillator (XTO) in combination with a divide by 14 cir- cuit. According to section “RF Front End” on page 4, the frequency of the crystal oscillator (f XTO) is defined by the RF input signal (f RFin) which also defines the operating frequency of the local oscillator (f LO). The basic clock cycle is TClk = 14/fXTO giving TClk = 2.066 µs for fRF =868.3 MHz and T Clk = 1.961 µs for fRF =915 MHz. T Clk controls the following application-relevant parameters: • Timing of the polling circuit including bit check • Timing of the analog and digital signal processing • Timing of the register programming • Frequency of the reset marker • IF filter center frequency (f IF0) Most applications are dominated by two transmission frequencies: f Transmit = 915 MHz is mainly used in USA, f Transmit = 868.3 MHz in Europe. In order to ease the usage of all TClk-dependent parameters on this electrical characteristics display three conditions for each parameter. • Application USA (f XTO = 7.14063 MHz, TClk = 1.961 µs) • Application Europe (f XTO = 6.77617 MHz, TClk =2.066 µs) for BIF = 600 kHz (f XTO = 6.77587 MHz, TClk =2.066 µs) for BIF = 300 kHz • Other applications The electrical characteristic is given as a function of T Clk. The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following for- mulas for further reference: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk |
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