8

5134E–SEEPR–3/08

AT24HC02B

Figure 5-6.

Output Acknowledge

6.

Device Addressing

The 2K EEPROM device requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation, as shown in Figure 6-1.

Figure 6-1.

Device Address

The device address word consists of a mandatory “1”, “0” sequence for the first four most signif-

icant bits as shown. This is common to all the EEPROM devices.

The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three

bits must compare to their corresponding hardwired input pins.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high, and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,

the chip will return to a standby state.

SCL

DATA IN

DATA OUT

START

ACKNOWLEDGE

9

8

1

MSB

2K

LSB

1

R/W

00

1