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AT24HC04BN-SH-T Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT24HC04BN-SH-T Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 19 page 3 5227E–SEEPR–11/08 AT24HC04B 1. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open- drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2 and A1 pins are device address inputs that must be hardwired for the AT24HC04B. As many as four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect. (Device addressing and Page addressing are discussed in detail under Device Addressing and Page Addressing, page 8). WRITE PROTECT (WP): The AT24HC04B has a WP pin that provides hardware data protec- tion. The WP pin allows normal read/write operations when connected to ground (GND). When the WP pin is connected to V CC, the write protection feature is enabled and operates as shown. Table 1-1. Write Protect WP Pin Status Part of the Array Protected 24HC04B At VCC Upper Half (2K) Array At GND Normal Read/Write Operations |
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