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AT24C256BY7-YH-T Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT24C256BY7-YH-T Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 24 page Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) • Internally Organized as 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years • Lead-free/Halogen-free Devices Available • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Waffle Pack and Bumped Wafers Description The AT24C256B provides 262,144 bits of serial electrically erasable and programma- ble read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8- lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V to 5.5V) version. Two-wire Serial EEPROM 256K (32,768 x 8) AT24C256B Rev. 5279B–SEEPR–3/08 Pin Configurations Pin Name Function A0–A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground A0 A1 A2 GND VCC WP SCL SDA 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 8 7 6 5 1 2 3 4 VCC WP SCL SDA A0 A1 A2 GND 8-lead PDIP 8-lead SOIC 8-lead dBGA2 Bottom View 8 7 6 5 1 2 3 4 VCC WP SCL SDA A0 A1 A2 GND 8-lead Ultra Thin SAP Bottom View A0 A1 A2 GND VCC WP SCL SDA 1 2 3 4 8 7 6 5 8-lead TSSOP |
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