AZ6123 datasheet(4/67 Pages) TI

Part #	AZ6123

Description	12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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Manufacturer	TI [Texas Instruments]

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RECOMMENDED OPERATING CONDITIONS

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage

3

3.3

3.6

V

CMOS Interface

1.65

1.8 to 3.3

3.6

V

DRVDD Output buffer supply voltage (1)

LVDS Interface

3

3.3

3.6

V

ANALOG INPUTS

Differential input voltage range

2

Vpp

VIC

Input common-mode voltage

1.5 ± 0.1

V

Voltage applied on VCM in external reference mode

1.45

1.5

1.55

V

CLOCK INPUT

ADS6125

1

125

ADS6124

1

105

FS

Input clock sample rate

MSPS

ADS6123

1

80

ADS6122

1

65

Sine wave, ac-Coupled

0.4

1.5

LVPECL, ac-Coupled

± 0.8

Input clock amplitude differential

Vpp

(VCLKP – VCLKM)

LVDS, ac-Coupled

± 0.35

LVCMOS, ac-Coupled

3.3

Input Clock duty cycle

35%

50%

65%

DIGITAL OUTPUTS

For CLOAD ≤ 5 pF and DRVDD ≥ 2.2

DEFAULT

V

strength

For CLOAD > 5 pF and DRVDD ≥ 2.2

MAXIMUM

Output buffer drive strength (2)

V

strength

MAXIMUM

For DRVDD < 2.2 V

strength

CMOS Interface, maximum buffer

10

strength

Maximum external load capacitance from each

LVDS Interface, without internal

5

CLOAD

pF

output pin to DRGND

termination

LVDS Interface, with internal

10

termination

RLOAD

Differential load resistance (external) between the LVDS output pairs

100

Ω

TA

Operating free-air temperature

-40

85

°C

(1)

For easy migration to next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.

(2)

See Output Buffer Strength Programmability in application section

4

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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

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