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CMP0417AA2 Datasheet(PDF) 10 Page - FIDELIX |
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CMP0417AA2 Datasheet(HTML) 10 Page - FIDELIX |
10 / 12 page CMP0417AAx-E CMOS LPRAM Revision 0.5 Aug. 2006 10 LOW POWER MODES Address /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tCW(2) tAS(3) tAW /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 1. Mode Register Set A0 A1 A2 A3 A4 A17 ~ A5 Array Refresh Area Half Selection Array On/Off on /ZZ 1 0 Array On/Off on /ZZ Reduced Memory Size Mode 1 Partial Array Refresh Mode (Default) 0 Type A3 Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) Top 1 Bottom (Default) 0 Type A2 Array Refresh Area RFU1) 1 0 ½ Array 0 1 1 0 A1 ¼ Array 1 Full Array (Default) 0 Type A0 2. MRS Update Reduced Memory Size Mode 1 Partial Array Refresh Mode (Default) 0 Type A3 1. RFU : Reserved for the Future Use |
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