FMP1617CA0(7)

CMOS LPRAM

Revision 0.1

Jun. 2006

5

AC OPERATING CONDITIONS

Input pulse level : 0.2 to VCC-0.2V

Input rising and falling time : 5ns

Input and output reference voltage : 0.5*VCCQ

30pf

1TTL

ns

20k

-

20k

-

tMRC

Maximum Cycle Time

Page

ns

-

10

-

10

tCP

ns

25

-

20

-

tPAA

Page Mode Address Access Time

ns

-

25

-

20

tPC

Page Mode Cycle Time

/CS High Pulse Width

ns

-

5

-

5

tOW

End Write to Output Low-Z

ns

-

0

-

0

tDH

Data Hold from Write Time

ns

-

20

-

20

tDW

Data to Write Time Overlap

ns

5

0

5

0

tWHZ

Write to Output High-Z

ns

-

0

-

0

tWR

Write Recovery Time

ns

-

50

-

50

tWP

Write Pulse Width

ns

-

60

-

50

tBW

/UB, /LB Valid to End of Write

ns

-

60

-

50

tAW

Address Valid to End of Write

ns

-

0

-

0

tAS

Address Set-up Time

ns

-

60

-

50

tCW

Chip Select to End of Write

ns

20k

70

20k

60

tWC

Write Cycle Time

Write

ns

-

5

-

5

tOH

Output Hold from Address Change

ns

5

0

5

0

tOHZ

Output Disable to High- Z Output

ns

5

0

5

0

tBHZ

/UB, /LB Disable to High- Z Output

ns

5

0

5

0

tHZ

Chip Disable to High- Z Output

ns

-

5

-

5

tOLZ

Output Enable to Low-Z Output

70ns

ns

-

10

-

10

tBLZ

/UB, /LB Enable to Low-Z Output

ns

-

10

-

10

tLZ

Chip Select to Low-Z Output

ns

70

-

60

-

tBA

/UB, /LB Access Time

ns

25

-

25

-

tOE

Output Enable to Valid Output

ns

70

-

60

-

tCO

Chip Select to Output

ns

70

-

60

-

tAA

Address Access Time

ns

20k

70

20k

60

tRC

Read Cycle Time

Read

Max

Min

Max

Min

60ns

Units

Speed Bins

Symbol

Parameter List

1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.