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FMP1617CAX Datasheet(PDF) 8 Page - FIDELIX |
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FMP1617CAX Datasheet(HTML) 8 Page - FIDELIX |
8 / 12 page FMP1617CAx CMOS LPRAM Revision 0.1 Jun. 2006 8 WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH) Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAS(3) tAW WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH) 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) WRITE CYCLE (1) (/WE controlled, /ZZ=VIH) Address /CS /UB, /LB /WE Data Out tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOW tWHZ Data in |
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