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5962-08A0101QXC Datasheet(PDF) 5 Page - ATMEL Corporation

Part # 5962-08A0101QXC
Description  Triple SpaceWire links High Speed Controller
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

5962-08A0101QXC Datasheet(HTML) 5 Page - ATMEL Corporation

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5
7737B–AERO–05/08
AT7911E
3.
Pin Description
Table 2. Pin description
Signal Name(1)(3)
Type(2)(4)
Function
5V
± 0.5V
max. output
current [mA]
3.3V
± 0.3V
max. output
current [mA]
load [pF]
HSEL*
I
Select host interface
HRD*
I
host interface read strobe
HWR*
I
host interface write strobe
HADR(7:0)
I
AT7911E register address lines. These address lines will be
used to access (address) the AT7911E registers.
HDATA(31:0)
IO/Z
AT7911E data
3
1.5
50
HACK
O/Z
host acknowledge. The AT7911E deasserts this output to
add waitstates to an AT7911E access. After AT7911E is
ready this output will be asserted.
3
1.5
50
HINTR*
O/Z
host interrupt request line
3
1.5
50
SMCSADR(3:0 )
I
Address. The binary value of these lines will be compared
with the value of the ID lines.
SMCSID(3:0)
I
ID lines: offers possibility to use sixteen AT7911E within one
HSEL*
HOSTBIGE
I
0: host I/F Little Endian
1: host I/F Big Endian
BOOTLINK
I
0: control by host
1: control by link
CMCS(1:0)*
O/Z
Communication memory select lines. These pins are
asserted as chip selects for the corresponding banks of the
communication memory.
6
3
25
CMRD*
O/Z
Communication memory read strobe. This pin is asserted
when the AT7911E reads data from memory.
6
3
25
CMWR*
O/Z
Communication memory write strobe. This pin is asserted
when the AT7911E writes to data memory.
6
3
25
CMADR(15:0)
O/Z
Communication memory address. The AT7911E outputs an
address on these pins.
6
3
25
CMDATA(31:0)
IOZ
Communication memory data. The AT7911E inputs and
outputs data from and to com. memory on these pins.
3
1.5
25
COCI
I
Communication interface 'occupied' input signal
COCO
O
Communication interface 'occupied' output signal
3
1.5
50
CAM
I
Communication interface arbitration master input signal
1: master
0: slave
CPUR*
O
CPU Reset Signal (can be used as user defined flag)
3
1.5
50
SES(3:0)*
O
Specific External Signals (can be used as user defined flags)
3
1.5
50
LDI1
I
Link Data Input channel 1
LSI1
I
Link Strobe Input channel 1
LDO1
O
Link Data Output channel 1
12
6
25


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