7

7752A–AERO–07/07

AT69170E

4.

Power-on mode

The AT69170E provides a READY output pin to indicate that the memory power-on sequence is

ended and that it is ready for use. This pin is available as an open-collector indicator of the

device’s reset status. It is driven Low while the device is in its power-on reset cycle and released

(tri-stated) when the cycle is complete.

It is recommended to pull-up this pin through a 4.7KOhms resistor.

5.

Standby mode

The AT69170E configurator enters a low-power standby mode whenever CE is asserted High.

In this mode, the output remains in a high-impedance state regardless of the state of the OE

input. Power Consumption is reduced to less than 5mA of current at 3.3V.

6.

Power down mode

In addition to the standby mode, the AT69170E implements a power down mode. In this mode,

the AT69170E consumes less than 1mA of current at 3.3V.

The power down mode is entered driving High the PWD input pin of the memory. For normal

operation of the memory, PWD pin shall be tied to a Low level.

7.

Programming mode - TWI mode

The AT69170E is a serial EEPROM memory used to load programmable devices. AT69170E

content is loaded and read thanks to a simple 2-wire serial interface (TWI). The programming

mode is entered if SER_EN is driven Low. In this mode the chip can be programmed by the

Two-Wire serial interface (TWI).

The 2-wire interface (TWI) is based on a simple synchronous protocol where one wire (CLOCK)

functions as a clock and shall be provided by the programmer and the second wire (DATA) is a

bi-directional signal and is used to provide data and control information. The system must pro-

vide a small pull-up current for the DATA line.

Information is transmitted on the serial bus in frames made of:

• A Start Condition

• A Data field with Acknowledge bits

• A Stop Condition

Each frame begins with a Start Condition and is ended with a Stop Condition. The data field is

made of an integer number of data bytes, each data byte consisting of 8 data bits followed by a

9th Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted byte.

7.1

TWI Frame Description

While writing to the AT69170E, the programmer is responsible for issuing the instruction and

data. The AT69170E acknowledges the transfer. While reading from the AT69170E, the pro-

grammer issues the instruction and acknowledges the data from the memory as necessary.

Data on the DATA pin may change only during the CLOCK Low time; whereas Start and Stop

Conditions are identified as transitions during the CLOCK High time.

All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop

Condition.