10

7747A–AERO–07/07

AT68166F/G

Figure 7. Write Cycle 1. WE Controlled, OE High During Write

Figure 8. Write Cycle 2. WE Controlled, OE Low

Figure 9. Write Cycle 3. CS Controlled

The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must

be activated to initiate a write and either signal can terminate a write by going in active mode. The data

input setup and hold timing should be referenced to the active edge of the signal that terminates the write.

E

E

ADDRESS

CSx

WEx

I/Os

OE

E

E

ADDRESS

CSx

WEx

I/Os

E

ADDRESS

CSx

WEx

I/Os