AT24C256C

7

8568A–SEEPR–11/08

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset

by following these steps:

a)

Create a start bit condition,

b)

Clock 9 cycles,

c)

Create another start bit followed by stop bit condition as shown below.

The device is ready for next communication after above steps has been completed.

Figure 4.

Software Reset

Start bit

Stop bit

Start bit

Dummy Clock Cycles

SCL

SDA

9

8

3

2

1

Figure 5.

Bus Timing

SCL

SDA IN

SDA OUT

t

F

t

HIGH

t

LOW

t

LOW

t

R

t

AA

t

DH

t

BUF

t

SU.STO

t

SU.DAT

t

HD.DAT

t

HD.STA

t

SU.STA

Figure 6.

Write Cycle Timing

t

wr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

Note:

1. The write cycle time t

internal clear/write cycle.