Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

DA28F640J5-150 Datasheet(PDF) 9 Page - Intel Corporation

Part # DA28F640J5-150
Description  5 Volt Intel StrataFlash짰 Memory
Download  51 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

DA28F640J5-150 Datasheet(HTML) 9 Page - Intel Corporation

Back Button DA28F640J5-150 Datasheet HTML 5Page - Intel Corporation DA28F640J5-150 Datasheet HTML 6Page - Intel Corporation DA28F640J5-150 Datasheet HTML 7Page - Intel Corporation DA28F640J5-150 Datasheet HTML 8Page - Intel Corporation DA28F640J5-150 Datasheet HTML 9Page - Intel Corporation DA28F640J5-150 Datasheet HTML 10Page - Intel Corporation DA28F640J5-150 Datasheet HTML 11Page - Intel Corporation DA28F640J5-150 Datasheet HTML 12Page - Intel Corporation DA28F640J5-150 Datasheet HTML 13Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 51 page
background image
28F320J5 and 28F640J5
Datasheet
9
Table 1.
Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
This address is latched duringa x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer
is turned off when BYTE# is high).
A1–A22
INPUT
ADDRESS INPUTS: Inputs for addresses duringread and program operations. Addresses are
internally latched duringa program cycle.
32-Mbit: A0–A21
64-Mbit: A0–A22
DQ0–DQ7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs
commands duringCommand User Interface (CUI) writes. Outputs array, query, identifier, or status
data in the appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled. Outputs DQ6–DQ0 are also floated when the Write State Machine (WSM) is busy. Check
SR.7 (status register bit 7) to determine WSM status.
DQ8–DQ15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS: Inputs data duringx16 buffer writes and programmingoperations.
Outputs array, query, or identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy.
CE0,
CE1,
CE2
INPUT
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see Table2onpage12, power reduces to standby
levels.
All timingspecifications are the same for these three signals. Device selection occurs with the first
edge of CE0,CE1,orCE2 that enables the device. Device deselection occurs with the first edge of
CE0,CE1,orCE2 that disables the device (see Table 2).
RP#
INPUT
RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode.
RP#-high enables normal operation. Exit from reset sets the device to read array mode. When
driven low, RP# inhibits write operations which provides data protection duringpower transitions.
RP# at VHH enables master lock-bit settingand block lock-bits configuration when the master
lock-bit is set. RP# = VHH overrides block lock-bits thereby enablingblock erase and
programming operations to locked memory blocks. Do not permanently connect RP# to VHH.
OE#
INPUT
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE#is activelow.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array
blocks. WE# is active low. Addresses and data are latched on the risingedge of the WE# pulse.
STS
OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the STATUS pin, see
the Configurations command. Tie STS to VCCQ with a pull-up resistor.
BYTE#
INPUT
BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on
DQ0–DQ7,while DQ8–DQ15 float. Address A0 selects between the high and low byte. BYTE# high
places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the
lowest order address.
VPEN
INPUT
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasingarray blocks, programmingdata, or
configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
VCC
SUPPLY
DEVICE POWER SUPPLY: With VCC ≤ VLKO, all write attempts to the flash memory are inhibited.
VCCQ
OUTPUT
BUFFER
SUPPLY
OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To
obtain output voltages compatible with system data bus voltages, connect VCCQ to the system
supply voltage.
GND
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.


Similar Part No. - DA28F640J5-150

ManufacturerPart #DatasheetDescription
logo
Intel Corporation
DA28F640J5-150 INTEL-DA28F640J5-150 Datasheet
641Kb / 53P
   StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
More results

Similar Description - DA28F640J5-150

ManufacturerPart #DatasheetDescription
logo
Intel Corporation
RC28F128J3A INTEL-RC28F128J3A_13 Datasheet
990Kb / 72P
   Intel StrataFlash짰 Memory
28F640L30 INTEL-28F640L30 Datasheet
1Mb / 100P
   1.8 Volt Intel StrataFlash짰 Wireless Memory with 3.0-Volt I/O (L30)
logo
Numonyx B.V
28F128L30 NUMONYX-28F128L30 Datasheet
1Mb / 102P
   StrataFlash짰 Wireless Memory
PF38F5070M0Y0B0 NUMONYX-PF38F5070M0Y0B0 Datasheet
2Mb / 139P
   StrataFlash짰 Cellular Memory
logo
Intel Corporation
28F128J3A INTEL-28F128J3A Datasheet
380Kb / 58P
   3 Volt Intel StrataFlash Memory
DT28F160S570 INTEL-DT28F160S570 Datasheet
318Kb / 51P
   5 VOLT FlashFile??MEMORY
logo
Numonyx B.V
JS28F128P30T85A NUMONYX-JS28F128P30T85A Datasheet
1Mb / 97P
   Numonyx??StrataFlash짰 Embedded Memory (P30)
logo
Intel Corporation
28F640C3 INTEL-28F640C3 Datasheet
177Kb / 18P
   3 Volt Intel Advanced Boot Block Flash Memory
PA28F400B5T80 INTEL-PA28F400B5T80 Datasheet
344Kb / 44P
   5 VOLT BOOT BLOCK FLASH MEMORY
28F640W30 INTEL-28F640W30 Datasheet
749Kb / 82P
   1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com