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DA28F640J5A-150 Datasheet(PDF) 9 Page - Intel Corporation |
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DA28F640J5A-150 Datasheet(HTML) 9 Page - Intel Corporation |
9 / 51 page 28F320J5 and 28F640J5 Datasheet 9 Table 1. Lead Descriptions Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched duringa x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). A1–A22 INPUT ADDRESS INPUTS: Inputs for addresses duringread and program operations. Addresses are internally latched duringa program cycle. 32-Mbit: A0–A21 64-Mbit: A0–A22 DQ0–DQ7 INPUT/ OUTPUT LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands duringCommand User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ6–DQ0 are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register bit 7) to determine WSM status. DQ8–DQ15 INPUT/ OUTPUT HIGH-BYTE DATA BUS: Inputs data duringx16 buffer writes and programmingoperations. Outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CE0, CE1, CE2 INPUT CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table2onpage12, power reduces to standby levels. All timingspecifications are the same for these three signals. Device selection occurs with the first edge of CE0,CE1,orCE2 that enables the device. Device deselection occurs with the first edge of CE0,CE1,orCE2 that disables the device (see Table 2). RP# INPUT RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection duringpower transitions. RP# at VHH enables master lock-bit settingand block lock-bits configuration when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enablingblock erase and programming operations to locked memory blocks. Do not permanently connect RP# to VHH. OE# INPUT OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. OE#is activelow. WE# INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the risingedge of the WE# pulse. STS OPEN DRAIN OUTPUT STATUS: Indicates the status of the internal state machine. When configured in level mode (default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to VCCQ with a pull-up resistor. BYTE# INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ0–DQ7,while DQ8–DQ15 float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. VPEN INPUT ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasingarray blocks, programmingdata, or configuring lock-bits. With VPEN ≤ VPENLK, memory contents cannot be altered. VCC SUPPLY DEVICE POWER SUPPLY: With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. VCCQ OUTPUT BUFFER SUPPLY OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To obtain output voltages compatible with system data bus voltages, connect VCCQ to the system supply voltage. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated. |
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Similar Description - DA28F640J5A-150 |
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