WS57C256F-35P datasheet(1/5 Pages) STMICROELECTRONICS

Part #	WS57C256F-35P

Description	HIGH SPEED 32K x 8 CMOS EPROM

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WS57C256F

3-13

VCC

A14

A13

A8

A9

A11

OE

A10

CE/PGM

O7

O6

O5

O4

O3

VPP

A12

A7

A6

A5

A4

A3

A2

A1

A0

O0

O1

O2

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A8

A9

A11

NC

OE

A10

CE/PGM

O7

O6

A6

A5

A4

A3

A2

A1

A0

NC

O0

O1 O2

NC O3 O4 O5

1

43

2

32 31 30

29

28

27

26

25

24

23

22

21

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20

TOP VIEW

Chip Carrier

CERDIP

PIN CONFIGURATION

HIGH SPEED 32K x 8 CMOS EPROM

KEY FEATURES

• Fast Access Time

• Immune to Latch-UP

— tACC = 35 ns

— Up to 200 mA

— tCE = 35 ns

• ESD Protection Exceeds 2000 Volts

• Low Power Consumption

• Available in 300 Mil DIP and PLDCC

— 200 µA Standby ICC

• DESC SMD No. 5962-86063

GENERAL DESCRIPTION

The WS57C256F is a High Performance 32K x 8 UV Erasable EPROM. It is manufactured using an advanced

CMOS process technology enabling it to operate at speeds as fast as 35 ns Address Access Time (tACC) and 35 ns

Chip Enable Time (tCE). It was designed utilizing WSI's patented self-aligned split gate EPROM cell, resulting in a

low power device with a very cost effective die size. The low standby power capability of this 256 K product (200 µA

in a CMOS interface environment) is especially attractive.

This product, with its high speed capability, is particularly appropriate for use with today's fast DSP processors and

high-clock-rate Microprocessors. The WS57C256F's 35 ns speed enables these advanced processors to operate

without introducing any undesirable wait states. The WS57C256F is also ideal for use in modem applications, and is

recommended for use in these applications by the leading modem chip set manufacturer.

The WS57C256F is available in a variety of package types including the space saving 300 Mil DIP, the surface

mount PLDCC, and other windowed and non-windowed options. And its standard JEDEC EPROM pinouts provide

for automatic upgrade density paths for current 64K and 128K EPROM users.

PINS

CE/

OE

A9

A0 VPP VCC OUTPUTS

MODE

PGM

Read

VIL

XX

VCC VCC

DOUT

Output

Disable

XVIH

XX

VCC VCC

High Z

Standby

VIH

XX

X

VCC VCC

High Z

Program

VIL

VIH

XX

VPP

2 VCC

DIN

Program

Verify

XVIL

XX

VPP2 VCC

DOUT

Program

Inhibit

VIH VIH

XX

VPP

2 VCC High Z

Signature3

VIL

VIL VH

2

VIL VCC VCC

23 H

4

VIL

VIL VH

2

VIH VCC VCC

EO H

5

MODE SELECTION

NOTES:

1. X can be VIL or VIH.

4. Manufacturer Signature.

2. VIH = VPP = 12.75 ± 0.25 V.

5. Device Signature.

3. A1 – A8, A10 – A14 = VIL.

PRODUCT SELECTION GUIDE

PARAMETER

WS57C256F-35

WS57C256F-45

WS57C256F-55

WS57C256F-70

Address Access Time (Max)

35 ns

45 ns

55 ns

70 ns

Output Enable Time (Max)

15 ns

20 ns

25 ns

30 ns

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WS57C256F-35P Datasheet(PDF) 1 Page - STMicroelectronics

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