THERMAL INFORMATION

APPLICATION INFORMATION

Hot-Plugging

Receiver Failsafe

SN65HVD1780

SN65HVD1781

SN65HVD1782

PARAMETER

TEST CONDITIONS

VALUE

UNIT

JEDEC high-K model

138

SOIC-8

JEDIC low-K model

242

°C/W

JEDEC high-K model

59

DIP-8

JEDIC low-K model

128

SOIC-8

62

°C/W

DIP-8

39

SOIC-8

61

°C/W

DIP-8

61

75

95

115

Power dissipation

mW

290

320

400

Thermal-shutdown junction temperature

170

°C

(1)

Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: 1 Mbps.

These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for

hot-pluggable applications are power-up, power-down glitch free operation, default disabled input/output pins,

and receiver failsafe. As shown in Figure 9, an internal Power-On Reset circuit keeps the driver outputs in a

high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This

ensures that no problems will occur on the bus pin outputs as the power supply turns on or turns off.

As shown in the device FUNCTION TABLE, the enable inputs have the feature of default disable on both the

driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R

pin until the associated controller actively drives the enable pins.

The differential receiver is "failsafe" to invalid bus states caused by open bus conditions such as, a disconnected

connector, shorted bus conditions caused by damaged cabling, or idle bus conditions that occur when no driver

is actively driving a valid RD-485 bus state on the network. In any of these cases, the differential receiver will

output a failsafe HIGH state, so that small noise signals do not cause problems at the receiver output.

Copyright © 2007–2008, Texas Instruments Incorporated

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Product Folder Link(s): SN65HVD1780 SN65HVD1781 SN65HVD1782