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WS57C71C-70 Datasheet(PDF) 1 Page - STMicroelectronics |
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WS57C71C-70 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 2 page PRODUCT SELECTION GUIDE PARAMETER WS57C71C-45 WS57C71C-55 WS57C71C-70 Address Access Time (Max) 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 20 ns 20 ns 30 ns WS57C71C 4-13 MILITARY HIGH SPEED 32K x 8 CMOS PROM/RPROM KEY FEATURES • Ultra-Fast Access Time • Immune to Latch-UP — 45 ns — Up to 200 mA • Low Power Consumption • ESD Protection Exceeds 2000V • Fast Programming • Available in 300 and 600 Mil DIP and CLLCC GENERAL DESCRIPTION The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The DIP version is packaged in a 300 mil wide DIP package saving board space for the user. MODE PINS CS1/ CS2 CS3 VCC OUTPUTS VPP Read VIL VIH VIL VCC DOUT Output Disable VIH XX VCC High Z Output XVIL XVCC High Z Disable Output XX VIH VCC High Z Disable Program VPP XVIH VCC DIN Program Verify VIL VIH VIL VCC DOUT Program Inhibit VPP XVIL VCC HIGH Z VCC A10 A11 A12 A13 A14 CS3 CS2 CS1/VPP O7 O6 O5 O4 O3 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A12 A13 A14 NC CS3 CS2 CS1/VPP O7 O6 A6 A5 A4 A3 A2 A1 A0 NC O0 O1 O2 NC O3 O4 O5 1 43 2 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TOP VIEW Chip Carrier CERDIP MODE SELECTION PIN CONFIGURATION Return to Main Menu |
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