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OMAP-L137 Datasheet(PDF) 6 Page - Texas Instruments |
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OMAP-L137 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 7 page Advisory 1.0.1 — ARM Data Cache in Write-Back Mode is Not Functional: Must Use Write-Through or Non-Cached Mode www.ti.com Table 3. Page Table C and B Bit Settings for the DCache C BIT B BIT DESCRIPTION ARM926EJ-S BEHAVIOR DCache disabled. Read from external memory. Write as a 0 0 Noncacheable, nonbufferable nonbuffered store(s) to external memory. DCache is not updated. DCache disabled. Read from external memory. Write as a 0 1 Noncacheable, bufferable buffered store(s) to external memory. DCache is not updated. DCache enabled: • Read hit - Read from DCache • Read miss - Linefill 1 0 Write-through • Write hit - Write to the DCache, and buffered store to external memory • Write miss - Buffered store to external memory DCache enabled: • Read hit - Read from DCache 1 1 Write-back • Read miss - Linefill • Write hit - Write to the DCache only • Write miss - Buffered store to external memory 6 OMAP-L137 SPRZ291 – October 2008 Silicon Revision 1.0 Submit Documentation Feedback |
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Similar Description - OMAP-L137_1 |
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