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TMP320F2802338S Datasheet(PDF) 8 Page - Texas Instruments |
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TMP320F2802338S Datasheet(HTML) 8 Page - Texas Instruments |
8 / 10 page Advisory — ADC: Initial Conversion www.ti.com Advisory ADC: Initial Conversion Revision(s) Affected 0 Details When the ADC conversions are initiated by any source of trigger, the first sample may not be the correct conversion result. Workaround(s) Discard the first sample at the beginning of every series of conversions. For instance, if the application calls for a given series of conversions, SOC0 →SOC1→SOC2, to initiate periodically, then setup the series instead as SOC0 →SOC1→SOC2→SOC3 and only use the last three conversions, ADCRESULT1, ADCRESULT2, ADCRESULT3, thereby discarding ADCRESULT0. Each application should validate this as acceptable in their application. Advisory Memory: Prefetching Beyond Valid Memory Revision(s) Affected 0 Details The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the prefetch occurs past the end of valid memory, then the CPU may receive an invalid opcode. Workaround The prefetch queue is 8x16 words in depth. Therefore, code should not come within 8 words of the end of valid memory. This restriction applies to all memory regions and all memory types (flash, OTP, SARAM) on the device. Prefetching across the boundary between two valid memory blocks is ok. Example 1: M1 ends at address 0x7FF and is not followed by another memory block. Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8-0x7FF should not be used for code. Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can be stored up to and including address 0x3FF. Code can also cross into M1 up to and including address 0x7F7. 8 TMS320x2802x Piccolo MCU Silicon Errata SPRZ292 – December 2008 Submit Documentation Feedback |
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