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HDSP-981 Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED |
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HDSP-981 Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED |
3 / 8 page 3 Figure 1. Timing diagram. Figure 2. Block diagram. tSETUP tHOLD tW tTLH DATA INPUT (LOW LEVEL DATA) 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 10% 90% DATA INPUT (HIGH LEVEL DATA) ENABLE INPUT LATCH MEMORY 4 6 4 DP DP 3 X8 2 X4 1 X2 8 5 7 BLANKING(3) CONTROL GROUND DP(2) INPUT LOGIC ENABLE VCC X1 MATRIX DECODER LED MATRIX DRIVER LED MATRIX TRUTH TABLE X8 L L L L L L L L H H H H H H H H X4 L L L L H H H H L L L L H H H H X2 L L H H L L H H L L H H L L H H X1 L H L H L H L H L H L H L H L H BCD DATA[1] NUMERIC DECIMAL PT.[2] ON OFF LOAD DATA LATCH DATA DISPLAY–ON DISPLAY–OFF VDP = L VDP = H VE = L VE = H VB = L VB = H ENABLE[1] BLANKING[3] (BLANK) (BLANK) •••• (BLANK) (BLANK) HEXADECIMAL NOTES: 1. H = LOGIC HIGH; L = LOGIC LOW. WITH THE ENABLE INPUT AT LOGIC HIGH, CHANGES IN BCD INPUT LOGIC LEVELS HAVE NO EFFECT UPON DISPLAY MEMORY, DISPLAYED CHARACTER, OR DP. 2. THE DECIMAL POINT INPUT, DP, PERTAINS ONLY TO THE NUMERIC DISPLAYS. 3. THE BLANKING CONTROL INPUT, B, PERTAINS ONLY TO THE HEXADECIMAL DISPLAYS. BLANKING INPUT HAS NO EFFECT UPON DISPLAY MEMORY. |
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